ISP1160
Embedded USB Host Controller
Philips Semiconductors
CS_N
A0
t
t
SLRL
SLWL
t
SHSL
t
RLRH
t
t
WHSH
RHSH
t
RHRL
T
RC
RD_N
t
RLDV
t
RHDZ
[
]
D 15:0
data
valid
data
valid
data
valid
data
valid
t
AS
t
WHWL
t
t
T
WC
AH
WL
WR_N
t
t
WDH
WDSU
data
valid
data
valid
data
valid
data
valid
data
valid
[
]
D 15:0
004aaa367
Fig 35. Programmed interface timing.
17.2 DMA timing
17.2.1 Single-cycle DMA timing
Table 74: Dynamic characteristics: single-cycle DMA timing
Symbol Parameter Conditions
Read/write timing
Min
Typ
Max
Unit
tRLRH
tRLDV
tRHDZ
tWSU
tWHD
tAHRH
tALRL
TDC
RD_N pulse width
33
26
0
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
read process data set-up time
read process data hold time
write process data set-up time
write process data hold time
DACK_N HIGH to DREQ HIGH
DACK_N LOW to DREQ LOW
DREQ cycle
-
20
-
5
0
-
72
-
-
21
-
[1]
-
tSHAH
RD_N/WR_N HIGH to
DACK_N HIGH
0
-
tRHAL
tDS
DREQ HIGH to DACK_N LOW
DREQ pulse spacing
0
-
-
-
-
ns
ns
146
[1] TDC = tRHAL + tDS + tALRL
9397 750 11371
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 04 July 2003
76 of 88
NXP [ NXP ]
