ISP1160
Embedded USB Host Controller
Philips Semiconductors
T
DC
DREQ
t
DS
t
ALRL
t
SHAH
t
RHAL
DACK_N
t
AHRH
t
t
RHDZ
RLDV
[
]
]
D 15:0
data
valid
(read)
[
D 15:0
data
valid
(write)
t
WSU
RD_N or
WR_N
004aaa371
t
WHD
Fig 36. Single-cycle DMA timing.
17.2.2 Burst mode DMA timing
Table 75: Dynamic characteristics: burst mode DMA timing
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Read/write timing (for 4-cycle and 8-cycle burst mode)
tRLRH
tRHRL
WR_N/RD_N LOW pulse width
42
60
-
-
-
-
ns
ns
WR_N/RD_N HIGH to next
WR_N/RD_N LOW
TRC
WR_N/RD_N cycle
102
22
0
-
-
-
-
ns
ns
ns
tSLRL
tSHAH
RD_N/WR_N LOW to DREQ LOW
64
-
RD_N/WR_N HIGH to
DACK_N HIGH
tSLAL
TDC
DREQ HIGH to DACK_N LOW
DREQ cycle
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
[1]
-
tDS(read) DREQ pulse spacing (read)
tDS(read) DREQ pulse spacing (read)
tDS(write) DREQ pulse spacing (write)
tDS(write) DREQ pulse spacing (write)
4-cycle burst mode
8-cycle burst mode
4-cycle burst mode
8-cycle burst mode
105
150
72
167
0
tRLIS
RD_N/WR_N LOW to EOT LOW
[1] TDC = tSLAL + (4 or 8)TRC + tDS
9397 750 11371
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 04 July 2003
77 of 88
NXP [ NXP ]
