ISP1160
Embedded USB Host Controller
Philips Semiconductors
17.1 Programmed I/O timing
Table 73: Dynamic characteristics: programmed interface timing
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tAS
address set-up time before
WR_N HIGH
5
-
-
ns
tAH
address hold time after WR_N HIGH
8
-
-
ns
Read timing
tSHSL
first RD_N/WR_N after A0 HIGH
CS_N LOW to RD_N LOW
RD_N HIGH to CS_N HIGH
RD_N LOW pulse width
RD_N HIGH to next RD_N LOW
RD_N cycle
300
0
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
tSLRL
-
tRHSH
tRLRH
tRHRL
0
-
33
110
143
3
-
-
TRC
-
tRHDZ
tRLDV
RD_N data hold time
22
32
RD_N LOW to data valid
-
Write timing
tWL
WR_N LOW pulse width
WR_N HIGH to next WR_N LOW
WR_N cycle
26
110
136
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
tWHWL
TWC
tSLWL
CS_N LOW to WR_N LOW
WR_N HIGH to CS_N HIGH
WR_N data set-up time
WR_N data hold time
tWHSH
tWDSU
tWDH
0
5
8
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© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 04 July 2003
75 of 88
NXP [ NXP ]
