ISP1160
Embedded USB Host Controller
Philips Semiconductors
13. Power-on reset (POR)
When VCC is directly connected to the RESET_N pin, the internal pulse width (tPORP
)
will be typically (600 ns to 1000 ns) + X, when VCC is 3.3 V. The time X depends on
how fast VCC is rising with respect to Vtrip (2.03 V). The time X is decided by the
external power supply circuit.
To give a better view of the functionality, Figure 33 shows a possible curve of
VCC(POR) with dips at t2-t3 and t4-t5. If the dip at t4-t5 is too short (that is, <11 µs), the
internal POR pulse will not react and will remain LOW. The internal POR starts with a
1 at t0. At t1, the detector will see the passing of the trip level and a delay element will
add another tPORP before it drops to 0.
The internal POR pulse will be generated whenever VCC(POR) drops below Vtrip for
more than 11 µs.
Even if VCC is 5.0 V, Vtrip still remains at 2.03 V. This is because the 5 V tolerant pads
and on-chip voltage regulator ensure that 3.3 V is going to the internal POR circuitry
by clipping the voltage above 3.3 V.
V
CC(POR)
V
trip
t1
t3
t0
t4 t5
t2
(1)
PORP
t
t
PORP
PORP
004aaa389
(1) PORP = power-on reset pulse.
Fig 33. Internal POR timing.
The RESET_N pin can be either connected to VCC (using the internal POR circuit) or
externally controlled (by the microprocessor, ASIC, and so on). Figure 34 shows the
availability of the clock with respect to the external POR.
POWER-ON RESET
EXTERNAL CLOCK
004aaa365
A
Stable external clock is available at A.
Fig 34. Clock with respect to the external POR.
9397 750 11371
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 04 July 2003
70 of 88
NXP [ NXP ]
