ISP1160
Embedded USB Host Controller
Philips Semiconductors
ITL0BufferDone and ITL0BufferFull bits will be cleared automatically. This also
applies to the ITL1 buffer because ITL0 and ITL1 are Ping-Pong structured buffers. To
recover from this state, a power-on reset or software reset will have to be applied.
9.5.1 Time domain behavior
In example 1 (Figure 21), the CPU is fast enough to read back and download a
scenario before the next interrupt. Note that on the ISO interrupt of frame N:
• The ISO packet for frame N + 1 will be written
• The AT packet for frame N + 1 will be written.
AT
interrupt
traffic
on USB
SOF
(frame N)
(frame N + 1)
(frame N + 2)
(frame N + 3)
MGT954
ISO
interrupt
read ISO_A(N − 1) write ISO_A(N + 1)
read AT(N)
write AT(N + 1)
Fig 21. HC time domain behavior: example 1.
In example 2 (Figure 22), the microprocessor is still busy transferring the AT data
when the ISO interrupt of the next frame (N + 1) is raised. As a result, there will be no
AT traffic in frame N + 1. The HC does not raise an AT interrupt in frame N + 1. The
AT part is simply postponed until frame N + 2. On the AT N + 2 interrupt, the transfer
mechanism is back to the normal operation. This simple mechanism ensures, among
other things, that Control transfers are not dropped systematically from the USB in
case of an overloaded microprocessor.
(frame N)
(frame N + 1)
(frame N + 2)
(frame N + 3)
MGT955
Fig 22. HC time domain behavior: example 2.
In example 3 (Figure 23), the ISO part is still being written while the Start of Frame
(SOF) of the next frame has occurred. This will result in undefined behavior for the
ISO data on the USB bus in frame N + 1 (depending on whether the exact timing data
is corrupted or not). The HC should not raise an AT interrupt in frame N + 1.
9397 750 11371
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 04 July 2003
30 of 88
NXP [ NXP ]
