NXP Semiconductors
HEF4520B
Dual binary counter
5. Pinning information
5.1 Pinning
HEF4520B
1CP0
1CP1
1Q0
1Q1
1Q2
1Q3
1MR
V
SS
1
2
3
4
5
6
7
8
001aae704
16 V
DD
15 2MR
14 2Q3
13 2Q2
12 2Q1
11 2Q0
10 2CP1
9
2CP0
Fig 4.
Pin configuration
5.2 Pin description
Table 2.
Symbol
1CP0, 2CP0
1CP1, 2CP1
1Q0 to 1Q3
1MR, 2MR
V
SS
2Q0 to 2Q3
V
DD
Pin description
Pin
1, 9
2, 10
3, 4, 5, 6
7, 15
8
11, 12, 13, 14
16
Description
clock input (LOW-to-HIGH triggered)
clock input (HIGH-to-LOW triggered)
output
master reset input
ground supply voltage
output
supply voltage
6. Functional description
Table 3.
nCP0
L
X
H
X
[1]
Function table
nCP1
H
X
L
X
nMR
L
L
L
L
L
L
H
Mode
counter advances
counter advances
no change
no change
no change
no change
nQ0 to nQ3 = LOW
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= positive-going transition;
= negative-going transition.
HEF4520B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 18 November 2011
3 of 14
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