HEF4520B
NXP Semiconductors
Dual binary counter
t
W
V
I
90 %
90 %
negative
pulse
V
V
V
M
M
10 %
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
90 %
positive
pulse
V
M
M
10 %
10 %
0 V
t
W
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a. Input waveforms
V
DD
V
V
O
I
G
DUT
C
L
R
T
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b. Test circuit
Test data is given in Table 9.
Definitions for test circuit:
DUT = Device Under Test;
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 6. Test circuit for measuring switching times
Table 9.
Measurement points and test data
Supply voltage
Input
VI
Load
CL
VM
tr, tf
5 V to 15 V
VDD
0.5VI
20 ns
50 pF
HEF4520B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 18 November 2011
8 of 14
NXP [ NXP ]
