HEF4520B
NXP Semiconductors
Dual binary counter
Table 7.
Dynamic characteristics …continued
VSS = 0 V; Tamb = 25 C; for test circuit see Figure 6; unless otherwise specified.
Symbol Parameter
Conditions
VDD
5 V
Extrapolation formula
83 ns + (0.55 ns/pF)CL
39 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)CL
10 ns + (1.00 ns/pF)CL
9 ns + (0.42 ns/pF)CL
6 ns + (0.28 ns/pF)CL
Min
-
Typ
110
50
40
60
30
20
30
15
10
30
15
10
15
10
8
Max Unit
[1]
tPLH LOW to HIGH
nCP0, nCP1 nQn;
220
ns
propagation delay see Figure 5
10 V
15 V
5 V
-
100
ns
-
80
ns
[1]
tt
transition time
pulse width
nQn; see Figure 5
-
120
ns
10 V
15 V
5 V
-
60
40
-
ns
-
ns
tW
nCP0 input LOW;
minimum width;
see Figure 5
60
30
20
60
30
20
30
20
16
50
30
20
50
30
20
50
30
20
8
ns
10 V
15 V
5 V
-
ns
-
ns
nCP1 input HIGH;
minimum width;
see Figure 5
-
ns
10 V
15 V
5 V
-
ns
-
ns
nMR input HIGH;
minimum width;
see Figure 5
-
ns
10 V
15 V
5 V
-
ns
-
ns
tsu
set-up time
nCP0 nCP1;
see Figure 5
25
15
10
25
15
10
25
15
10
16
30
40
-
ns
10 V
15 V
5 V
-
ns
-
ns
nCP1 nCP0;
see Figure 5
-
ns
10 V
15 V
5 V
-
ns
-
ns
trec
recovery time
see Figure 5
-
ns
10 V
15 V
5 V
-
ns
-
ns
fmax
maximum
frequency
nCP0, nCP1;
see Figure 5
-
MHz
MHz
MHz
10 V
15 V
15
20
-
-
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
Table 8.
Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol
Parameter
VDD
5 V
Typical formula for PD (W)
PD = 850 fi + (fo CL) VDD
Where:
2
PD
dynamic power
dissipation
fi = input frequency in MHz,
fo = output frequency in MHz,
CL = output load capacitance in pF,
2
10 V
15 V
PD = 3800 fi + (fo CL) VDD
2
PD = 10200 fi + (fo CL) VDD
VDD = supply voltage in V,
(fo CL) = sum of the outputs.
HEF4520B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 18 November 2011
6 of 14
NXP [ NXP ]
