NXP Semiconductors
HEF4520B
Dual binary counter
4. Functional diagram
1Q0 3
1 1CP0
1Q1 4
2 1CP1
1Q2 5
1Q3 6
7 1MR
2Q0 11
9 2CP0
2Q1 12
10 2CP1
2Q2 13
2Q3 14
15 2MR
001aae698
Fig 1.
Functional diagram
1
nCP0
nCP1
nMR
1
nQ0
nQ1
nQ2
nQ
3
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
001aae707
Fig 2.
Timing diagram
nQ0
nQ1
nQ2
nQ3
Q
nCP1
FF 1
T
CD Q
T
FF 2
Q
FF 3
T
CD Q
Q
FF 4
T
CD Q
Q
nCP0
CD Q
nMR
001aae705
Fig 3.
Logic diagram for one counter
HEF4520B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 18 November 2011
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