HEF4017B-Q100
NXP Semiconductors
5-stage Johnson decade counter
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Tamb = 25 C; VSS = 0 V; for test circuit see Figure 10
Symbol Parameter Conditions
tPHL HIGH to LOW
propagation delay see Figure 7
VDD
Extrapolation formula[1]
Min Typ Max Unit
CP0, CP1 Q0 to Q9; 5 V
113 ns + (0.55 ns/pF)CL
44 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)CL
118 ns + (0.55 ns/pF)CL
44 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)CL
88 ns + (0.55 ns/pF)CL
39 ns + (0.23 ns/pF)CL
27 ns + (0.16 ns/pF)CL
98 ns + (0.55 ns/pF)CL
39 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)CL
98 ns + (0.55 ns/pF)CL
39 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)CL
83 ns + (0.55 ns/pF)CL
34 ns + (0.23 ns/pF)CL
27 ns + (0.16 ns/pF)CL
103 ns + (0.55 ns/pF)CL
44 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)CL
10 ns + (1.00 ns/pF)CL
9 ns + (0.42 ns/pF)CL
6 ns + (0.28 ns/pF)CL
-
140 280 ns
10 V
15 V
5 V
-
55
40
110 ns
80 ns
-
CP0, CP1 Q5-9;
see Figure 7
-
145 290 ns
10 V
15 V
5 V
-
55
40
110 ns
80 ns
-
MR Q1 to Q9;
see Figure 8
-
115 230 ns
10 V
15 V
-
50
35
100 ns
70 ns
-
tPLH
LOW to HIGH
CP0, CP1 Q0 to Q9; 5 V
-
125 250 ns
propagation delay see Figure 7
10 V
15 V
5 V
-
50
40
100 ns
80 ns
-
CP0, CP1 Q5-9;
see Figure 7
-
125 250 ns
10 V
15 V
5 V
-
50
40
100 ns
80 ns
-
MR Q5-9;
see Figure 8
-
110 220 ns
10 V
15 V
5 V
-
45
35
90
70
ns
ns
-
MR Q0;
see Figure 8
-
130 260 ns
10 V
15 V
5 V
-
55
40
60
30
20
45
20
10
40
20
10
105 ns
75 ns
120 ns
-
[2]
tt
transition time
hold time
see Figure 7
-
10 V
15 V
5 V
-
60
40
-
ns
ns
ns
ns
ns
ns
ns
ns
-
th
CP0 CP1;
90
40
20
80
40
30
see Figure 9
10 V
15 V
5 V
-
-
CP1 CP0;
see Figure 9
-
10 V
15 V
-
-
HEF4017B_Q100
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© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 4 June 2014
8 of 18
NXP [ NXP ]
