HEF4017B-Q100
NXP Semiconductors
5-stage Johnson decade counter
5.2 Pin description
Table 2.
Symbol
Q0 to Q9
VSS
Pin description
Pin
Description
3, 2, 4, 7, 10, 1, 5, 6, 9, 11
decoded output
8
ground supply voltage
carry output (active LOW)
Q5-9
12
13
14
15
16
CP1
clock input (HIGH-to-LOW edge-triggered)
clock input (LOW-to-HIGH edge-triggered)
master reset input
CP0
MR
VDD
supply voltage
6. Functional description
Table 3.
Function table [1]
MR
H
L
CP0
X
CP1
X
Operation
Q0 = Q5-9 = H; Q1 to Q9 = L
counter advances
counter advances
no change
H
L
L
L
L
X
L
X
H
no change
L
H
no change
L
L
no change
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= positive-going transition; = negative-going transition.
HEF4017B_Q100
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© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 4 June 2014
4 of 18
NXP [ NXP ]
