HEF4017B-Q100
NXP Semiconductors
5-stage Johnson decade counter
11. Waveforms
V
I
CP0 input
V
V
V
M
M
SS
V
I
CP1 input
V
SS
t
t
t
t
PHL
PLH
PLH
PHL
V
OH
Q1 - Q9
output
V
M
V
OL
V
OH
Q0, Q5 - Q9
output
V
M
V
OL
t
t
TLH
THL
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Conditions: CP1 = LOW, while CP0 triggers on a LOW-to-HIGH transition. CP1 triggers on a HIGH-to-LOW transition;
The shaded areas indicate where the output state is set by the input count.
Measurement points given in Table 9.
Fig 7. Waveforms showing the propagation delays for CP0, CP1 to Qn, Q5-9 outputs and the output transition
times
HEF4017B_Q100
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© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 4 June 2014
10 of 18
NXP [ NXP ]
