HEF4017B-Q100
NXP Semiconductors
5-stage Johnson decade counter
1/f
max
t
W
V
I
CP0 input
V
V
M
M
V
SS
1/f
max
V
I
CP1 input
V
SS
t
W
t
rec
V
I
MR input
V
M
V
SS
t
W
V
OH
Q1 - Q9
output
V
M
M
V
OL
t
t
PHL
PLH
V
OH
Q0, Q5 - Q9
output
V
V
OL
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Conditions: CP1 = LOW, while CP0 triggers on a LOW-to-HIGH transition, tW and trec are measured when CP0 = HIGH and
CP1 triggers on a HIGH-to-LOW transition.
The shaded areas indicate where the output state is set by the input count.
Measurement points given in Table 9.
Fig 8. Waveforms showing the minimum pulse width for CP0, CP1 and MR input; the maximum frequency for
CP0 and CP1 input; the recovery time for MR and the MR input to Qn and Q5-9 output propagation delays
V
I
CP0 input
V
V
M
M
V
SS
t
t
h
h
V
I
CP1 input
V
V
M
M
V
SS
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Hold times are shown as positive values, but may be specified as negative values;
Measurement points given in Table 9.
Fig 9. Waveforms showing hold times for CP0 to CP1 and CP1 to CP0
Table 9.
Measurement points
Supply voltage
VDD
Input
VM
Output
VM
5 V to 15 V
0.5VDD
0.5VDD
HEF4017B_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 4 June 2014
11 of 18
NXP [ NXP ]
