NXP Semiconductors
74HC10-Q100; 74HCT10-Q100
Triple 3-input NAND gate
Table 7.
Dynamic characteristics
GND = 0 V; C
L
= 50 pF; for test circuit see
Figure 7.
Symbol Parameter
Conditions
Min
74HCT10-Q100
t
pd
propagation delay nA, nB to nY; see
V
CC
= 4.5 V
V
CC
= 5.0 V; C
L
= 15 pF
t
t
C
PD
transition time
power dissipation
capacitance
V
CC
= 4.5 V; see
per package;
V
I
= GND to V
CC
1.5 V
25
C
Typ
Max
40 C
to +125
C
Unit
Max
(85
C)
Max
(125
C)
-
-
-
-
14
11
7
14
24
-
15
-
30
-
19
-
36
-
22
-
ns
ns
ns
pF
[1]
[2]
[3]
t
pd
is the same as t
PHL
and t
PLH
.
t
t
is the same as t
THL
and t
TLH
.
C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC2
f
i
N +
(C
L
V
CC2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC2
f
o
) = sum of outputs.
11. Waveform and test circuit
9
O
Q$ Q% Q& LQSXW
*1'
9
2+
Q<RXWSXW
9
2/
9
0
W
3+/
9
<
9
0
9
;
W
7+/
W
7/+
DDD
W
3/+
Measurement points are given in
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 6.
Table 8.
Type
Input to output propagation delays
Measurement points
Input
V
M
0.5V
CC
1.3 V
Output
V
M
0.5V
CC
1.3 V
V
X
0.1V
CC
0.1V
CC
V
Y
0.9V
CC
0.9V
CC
74HC10-Q100
74HCT10-Q100
74HC_HCT10_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2013
6 of 13
PHILIPS [ NXP SEMICONDUCTORS ]
