NXP Semiconductors
74HC10-Q100; 74HCT10-Q100
Triple 3-input NAND gate
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
E
v
M
A
Z
14
8
Q
A
2
pin 1 index
A
1
θ
L
p
L
(A
3
)
A
1
e
b
p
7
w
M
detail X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A
max.
1.1
A
1
0.15
0.05
A
2
0.95
0.80
A
3
0.25
b
p
0.30
0.19
c
0.2
0.1
D
(1)
5.1
4.9
E
(2)
4.5
4.3
e
0.65
H
E
6.6
6.2
L
1
L
p
0.75
0.50
Q
0.4
0.3
v
0.2
w
0.13
y
0.1
Z
(1)
0.72
0.38
θ
8
o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT402-1
REFERENCES
IEC
JEDEC
MO-153
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 9.
Package outline SOT402-1 (TSSOP14)
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
74HC_HCT10_Q100
Product data sheet
Rev. 1 — 21 February 2013
9 of 13
PHILIPS [ NXP SEMICONDUCTORS ]
