NXP Semiconductors
74HC10-Q100; 74HCT10-Q100
Triple 3-input NAND gate
4. Functional diagram
1
1
2
13
3
4
5
9
10
11
1A
1B
1C
2A
2B
2C
3A
3B
3C
mna757
2
1Y
12
13
3
2Y
6
4
5
&
12
&
6
A
3Y
8
9
10
11
mna759
&
8
B
C
Y
mna758
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram for one gate
5. Pinning information
5.1 Pinning
+&4
+&74
$
%
$
%
&
<
*1'
DDD
9
&&
&
<
&
%
$
<
+&4
+&74
$
%
$
%
&
<
*1'
DDD
9
&&
&
<
&
%
$
<
Fig 4.
Pin configuration SO14
Fig 5.
Pin configuration TSSOP14
5.2 Pin description
Table 2.
Symbol
1A, 2A, 3A
1B, 2B, 3B
GND
1C, 2C, 3C
1Y, 2Y, 3Y
V
CC
Pin description
Pin
1, 3, 9
2, 4, 10
7
13, 5, 11
12, 6, 8
14
Description
data input
data input
ground (0 V)
data input
data output
supply voltage
74HC_HCT10_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2013
2 of 13
PHILIPS [ NXP SEMICONDUCTORS ]
