NXP Semiconductors
74HC10-Q100; 74HCT10-Q100
Triple 3-input NAND gate
V
I
negative
pulse
GND
t
W
90 %
V
M
10 %
t
f
t
r
t
r
t
f
90 %
V
M
10 %
t
W
V
CC
G
VI
VO
V
M
V
I
positive
pulse
GND
V
M
DUT
RT
CL
001aah768
Test data is given in
Definitions test circuit:
R
T
= termination resistance should be equal to output impedance Z
o
of the pulse generator.
C
L
= load capacitance including jig and probe capacitance.
Fig 7.
Table 9.
Type
Test circuit for measuring switching times
Test data
Input
V
I
t
r
, t
f
6.0 ns
6.0 ns
V
CC
3.0 V
Load
C
L
15 pF, 50 pF
15 pF, 50 pF
t
PLH
, t
PHL
t
PLH
, t
PHL
Test
74HC10-Q100
74HCT10-Q100
74HC_HCT10_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2013
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