NXP Semiconductors
74HC109-Q100; 74HCT109-Q100
Dual JK flip-flop with set and reset; positive-edge-trigger
6. Functional description
Table 3.
Function selection
Input
nSD
Asynchronous set
Asynchronous reset
Undetermined
Toggle
Load 0 (reset)
Load 1 (set)
Hold no change
[1]
H = HIGH voltage level
h = HIGH voltage level one set-up time before the LOW-to-HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time before the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time before the LOW-to-HIGH CP transition
X = don’t care
= LOW-to-HIGH CP transition
Operating modes
Output
nRD
H
L
L
H
H
H
H
nCP
X
X
X
nJ
X
X
X
h
l
h
l
nK
X
X
X
l
l
h
h
nQ
H
L
H
q
L
H
q
nQ
L
H
H
q
H
L
q
L
H
L
H
H
H
H
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
Min
0.5
-
-
-
-
50
65
Max
+7
20
20
25
+50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
SO16 package
-
For SO16 package: above 70
C,
the value of P
tot
derates linearly with 8 mW/K.
74HC_HCT109_Q100
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 28 September 2016
4 of 17
PHILIPS [ NXP SEMICONDUCTORS ]
