NXP Semiconductors
74HC109-Q100; 74HCT109-Q100
Dual JK flip-flop with set and reset; positive-edge-trigger
Table 7.
Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit, see
Figure 7.
Symbol Parameter
t
W
pulse width
Conditions
nCP HIGH or LOW;
see
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
nSD, nRD HIGH or LOW;
see
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
t
rec
recovery time nSD, nRD to nCP;
see
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
t
su
set-up time
nJ and nK to nCP;
see
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
t
h
hold time
nJ and nK to nCP;
see
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
f
max
maximum
frequency
nCP; see
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 5 V; C
L
= 15 pF
V
CC
= 6.0 V
C
PD
power
dissipation
capacitance
C
L
= 50 pF; f = 1 MHz;
V
I
= GND to V
CC
25
C
Min Typ
[1]
Max
40 C
to +85
C
Min
Max
40 C
to +125
C
Min
Max
Unit
80
16
14
19
7
6
-
-
-
100
20
17
-
-
-
120
24
20
-
-
-
ns
ns
ns
80
16
14
14
5
4
-
-
-
100
20
17
-
-
-
120
24
20
-
-
-
ns
ns
ns
70
14
12
19
7
6
-
-
-
90
18
15
-
-
-
105
21
18
-
-
-
ns
ns
ns
70
14
12
17
6
5
-
-
-
90
18
15
-
-
-
105
21
18
-
-
-
ns
ns
ns
5
5
5
6
30
-
35
-
0
0
0
22
68
75
81
20
-
-
-
-
-
-
-
-
5
5
5
5
24
-
28
-
-
-
-
-
-
-
-
-
5
5
5
4
20
-
24
-
-
-
-
-
-
-
-
-
ns
ns
ns
MHz
MHz
MHz
MHz
pF
74HC_HCT109_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 28 September 2016
8 of 17
PHILIPS [ NXP SEMICONDUCTORS ]
