74HC109-Q100; 74HCT109-Q100
Dual JK flip-flop with set and reset; positive-edge-trigger
Rev. 1 — 28 September 2016
Product data sheet
1. General description
The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop
featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD)
inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active
LOW inputs and operate independently of the clock input. The nJ and nK inputs control
the state changes of the flip-flops as described in the mode select function table. The nJ
and nK inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition
for predictable operation. The JK design allows operation as a D-type flip-flop by
connecting the nJ and nK inputs together. Inputs include clamp diodes. It enables the use
of current limiting resistors to interface inputs to voltages in excess of V
CC
.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Input levels:
For 74HC109-Q100: CMOS level
For 74HCT109-Q100: TTL level
J and K inputs for easy D-type flip-flop
Toggle flip-flop or “do nothing” mode
Specified in compliance with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
PHILIPS [ NXP SEMICONDUCTORS ]
