NXP Semiconductors
74HC109-Q100; 74HCT109-Q100
Dual JK flip-flop with set and reset; positive-edge-trigger
5. Pinning information
5.1 Pinning
Fig 4.
Pin configuration for SO16
5.2 Pin description
Table 2.
Symbol
1RD, 2RD
1J, 2J
1K, 2K
1CP, 2CP
1SD, 2SD
1Q, 2Q
1Q, 2Q
GND
V
CC
Pin description
Pin
1, 15
2, 14
3, 13
4, 12
5, 11
6, 10
7, 9
8
16
Description
asynchronous reset input (active LOW)
synchronous input
synchronous input
clock input (LOW-to-HIGH; edge-triggered)
asynchronous set input (active LOW)
true flip-flop output
complement flip-flop output
ground (0 V)
supply voltage
74HC_HCT109_Q100
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Product data sheet
Rev. 1 — 28 September 2016
3 of 17
PHILIPS [ NXP SEMICONDUCTORS ]
