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SAA1305T 参数 Datasheet PDF下载

SAA1305T图片预览
型号: SAA1305T
PDF下载: 下载PDF文件 查看货源
内容描述: ON / OFF逻辑IC [On/off logic IC]
分类和应用: 商用集成电路光电二极管
文件页数/大小: 32 页 / 176 K
品牌: PANASONIC [ PANASONIC ]
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Philips Semiconductors  
Product specification  
On/off logic IC  
SAA1305T  
IMPEDANCE DETECTION  
Between detection and indication via the status register  
bit 6, a delay time is integrated (programmable via the  
impedance register bits 1 and 0; see Table 15). When the  
12VDD value is detected the EXNOR output will be set to  
logic 1 (active) and after the programmed delay time the  
status register bit 6 will be set to logic 1 (active). This event  
will also be indicated via pin CHI and (if enabled) pin RP.  
The impedance information (bit 6 is active) within the  
status register is present until the I2C-bus status is read.  
With the disappearance of the impedance information no  
further actions will be generated. Every impedance signal  
change during the delay time will restart the delay time.  
However an impedance detection is only possible in the  
event of a stable signal, at least for the programmed delay  
time. Setting the status register bit 6 with a repetition time  
which equals the ‘impedance delay time’ as long as  
input D1 stays in high-impedance state is implemented.  
Input D1 is a normal input with comparable behaviour like  
the other seven inputs. The only difference is an additional  
internal exclusive-NOR (EXNOR) connected between the  
two comparator outputs for high and low detection;  
see Fig.4. The EXNOR signal indicates, in combination  
with a special external circuit on input D1, a voltage of  
12VDD on this input.  
The simple input description for impedance detection is  
probably not the real solution, but helps to explain the  
function. Input D1 can be used as a normal input and for  
impedance detection as described in Table 2. For normal  
use the output Q acts like every other input, but for  
impedance detection the EXNOR output S is also  
important. Output S is linked to the status register bit 6 and  
indicates the 12VDD; see Table 5.  
12 V  
5 V  
O1  
S
ignition  
key  
100 k  
input D1  
3.5 V  
Q
10 kΩ  
R
100 kΩ  
O2  
S
1.5 V  
MGR203  
Fig.4 Simple input description for impedance detection.  
Table 2 Logic levels for impedance detection  
IGNITION KEY  
O1  
O2  
Q
S
12 V  
1
0
0
0
0
1
1
0 or 1  
0
0
1
0
Open-circuit (VI = 2.5 V)  
Ground (VI < 1.5 V)  
2004 Jan 15  
8
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