Philips Semiconductors
Product specification
On/off logic IC
SAA1305T
Table 5 Definition of the status register bits
BIT
DESCRIPTION
7
6
5
4
a logic 1 indicates a change on any of the inputs D7 to D0
a logic 1 indicates a 1⁄2VDD on input D1 (impedance detection)
a logic 1 indicates a reset after an oscillator fault
a logic 1 indicates a reset caused by a missed I2C-bus communication after a change information signal
(no communication between two Watchdog timer trigger pulses)
3
2
1
0
a logic 1 indicates a timer alarm
a logic 1 indicates a VL timer reset
a logic 1 indicates a device reset (via pin RES)
a logic 1 indicates a Watchdog timer reset
Table 6 Definition of the old and new register bits
BIT
DESCRIPTION
7
6
5
4
3
2
1
0
data of input D7
data of input D6
data of input D5
data of input D4
data of input D3
data of input D2
data of input D1
data of input D0
Table 7 Definition of the watch and alarm register bits (read mode); note 1
ADDRESS
DATA BITS
DESCRIPTION
hours of alarm
VALUES
DEFAULT
(HEX)
2
3
4
5
6
7
4 to 0
5 to 0
5 to 0
4 to 0
5 to 0
5 to 0
0 to 31
0 to 63
0 to 63
0 to 23
0 to 59
0 to 59
31
63
63
0
minutes of alarm
seconds of alarm
hours of watch
minutes of watch
seconds of watch
0
0
Note
1. The alarm is disabled by writing a time larger than 24:00:00. With the default values the alarm function is disabled.
2004 Jan 15
12
PANASONIC [ PANASONIC ]
