Philips Semiconductors
Product specification
On/off logic IC
SAA1305T
handbook, full pagewidth
SAA1305T
OPERABLE
RES = HIGH
I
2
C-bus error counter = 5
Watchdog timer error counter = 5
RUN
RESET
entry
(1)
event
(2)
event
(3)
; CHI
control register bit 0
STANDBY
entry
(4)
event
(5)
VL timer start
VL timer end
input D0 = logic 1
RES = LOW
oscillator fault
WAIT
entry
(6)
event
(5)
MGR202
(1)
(2)
(3)
(4)
(5)
(6)
See Section “Run mode entries”.
See Section “Run mode events”.
Possible events are: alterations on any of the inputs D0 to D7, an impedance detection, an alarm timer event and an oscillator fault.
See Section “Standby mode entries”.
Not available.
See Section “Wait mode entries”.
Fig.3 State diagram for IC modes.
R
UN MODE ENTRIES
•
Reset Watchdog timer error counter
•
Enable Watchdog timer
•
Enable V
L
timer function
•
Generate reset pulse
•
Disable reset generation via inputs D0 to D7 changes
(inclusive impedance detection) and watch compare
•
Reset
I
2
C-bus
interface
•
Set pin CHI to LOW (LOW = active)
•
Set pin ON/OFF to HIGH (ON is active).
R
UN MODE EVENTS
•
I
2
C-bus read and write commands
•
Watchdog timer reset
•
Missed
communication after a (CHI) change
information signal
I
2
C-bus
•
Oscillator fault.
W
AIT MODE ENTRIES
•
Disable Watchdog timer
•
Reset I
2
C-bus error counter
•
Reset Watchdog timer error counter
•
Start V
L
timer
•
Set pin CHI in 3-state
•
Set pin ON/OFF to LOW (OFF is active).
S
TANDBY MODE ENTRIES
•
Disable Watchdog timer
•
Reset Watchdog timer error counter
•
Reset I
2
C-bus error counter
•
Disable V
L
timer function
•
Enable reset generation via inputs D0 to D7 changes
(inclusive impedance detection) and watch compare
•
Set pin ON/OFF to LOW (OFF is active)
•
Set pin CHI in 3-state.
2004 Jan 15
6
PANASONIC [ PANASONIC SEMICONDUCTOR ]
