Philips Semiconductors
Product specification
On/off logic IC
SAA1305T
Power-on or system reset
After the system reset (rising edge on pin RES) all internal
registers are in a defined condition (see Table 4) and the
outputs are as shown in Table 3 for RES = HIGH.
The reset input (pin RES) is of the CMOS input levels type.
During a LOW level on pin RES the outputs are as shown
in Table 3 for RES = LOW.
Table 3 Logic levels for the reset input and oscillator failure
PIN
RES = LOW
RES = HIGH
OSCILLATOR FAILURE
RP
HIGH
HIGH (voltage on VDD
)
3-state
3-state [after a defined time (maximum reset time)]
ON/OFF
LED
LOW
LOW
HIGH
LOW
LOW
LOW
SDA
3-state
3-state
3-state (receiving mode if RP = LOW)
LOW (information for microcontroller)
3-state
LOW
CHI
Table 4 Defined condition after reset for the registers; RES = HIGH
REGISTER
Status register
New register
Old register
CONTENTS
02 (HEX)
all input latches are enabled
same levels as corresponding inputs during falling edge on pin RES
Control register
LED register
03 (HEX)
04 (HEX)
Alarm register
Watch register
FFFF (HEX); see Table 7
0000 (HEX)
Impedance register 03 (HEX)
2004 Jan 15
10
PANASONIC [ PANASONIC ]
