Philips Semiconductors
Product specification
On/off logic IC
SAA1305T
I2C-BUS INTERFACE COMMANDS
To terminate the stream of bytes, the master must not
acknowledge the last byte output, but must generate a
STOP condition. The output data is from consecutive byte
addresses, with the internal byte address counter
automatically incremented after each byte output. In the
event of higher read sequences than available data bytes,
the 7th and 8th bit content are 0 and the address counter
will generate a wrap around (output at address 0).
I2C-bus communication is only possible in the run mode.
Read mode operations
Only the sequential read mode is possible. The IC starts
after every device select (code 48) to output data 1.
However, in this event the master does acknowledge the
data output and the IC continues to output the next data in
sequence; see Figs 6 and 7.
The definitions of the bits are given in Tables 5, 6 and 7.
acknowledge
acknowledge
acknowledge
no acknowledge
handbook, full pagewidth
S
DEVICE SELECT
DATA 1
DATA N P
START
condition
STOP
condition
R/W
MGR221
Fig.6 I2C-bus read mode sequence.
handbook, full pagewidth
START
DEVICE SELECT
byte
STATUS
0
OLD
1
NEW
2
WATCH
STOP
3, 4, 5, 6, 7
MGR222
Fig.7 I2C-bus read data sequence.
11
2004 Jan 15
PANASONIC [ PANASONIC ]
