Philips Semiconductors
Product specification
On/off logic IC
SAA1305T
Reset time
The pulse time on pin RP is selectable via an I2C-bus
command; see Table 8. The default value after Power-on
reset is the longest time (20 ms). Selectable pulse times
via the control register are: 1, 5, 10 and 20 ms.
handbook, halfpage
D0
D1
CHI
RP
1
2
24
23
22
21
20
19
18
D2
LED
With the rising edge of the reset pulse all inputs, except the
Watchdog timer and VL timer, are disabled until the
I2C-bus command ENABLE-RESET. Each pulse on
pin RP resets the internal I2C-bus interface.
3
V
D3
4
DD
D4
SCL
5
V
D5
6
SS
On/off
SAA1305T
D6
SDA
7
The output signal on pin ON/OFF remains HIGH after a
trigger event. Trigger sources are:
D7
8
17 XTAL2
ON/OFF
RES
WD
XTAL1
OSC2
OSC1
TST
9
16
15
14
13
• Alterations on any of the inputs D0 to D7
• An impedance detection
10
11
• A device reset
• A VL (is an undervoltage) timer or alarm timer event
• An oscillator fault.
TS 12
MGR201
In the event of a five time failed Watchdog timer trigger or
missed I2C-bus read sequence (after a change information
indication), an internal logic circuit will reset pin ON/OFF
and set the IC in the standby mode. It is also possible to
control pin ON/OFF during the run mode via an I2C-bus
command (see Table 8, bit 1). In principal two stable IC
modes are possible; see Fig.3:
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
1. Standby mode: an oscillator fault and the following IC
function groups can trigger a reset pulse to enter the
run mode;
Figure 1 shows the block diagram for the SAA1305T.
Details are explained in the subsequent sections.
a) Watch (alarm timer).
b) Supply (device reset).
Watch and alarm functions
An internal RAM (watch register) counts automatically the
seconds for one-day (one-day reset also automatically).
The watch register can be set and read from the I2C-bus.
An alarm function is possible via a second RAM (alarm
register) and is programmable via the I2C-bus. The alarm
timer triggers pin CHI and if enabled the reset pulse on
pin RP. After a device reset the content of the alarm
register is FFFFH (alarm function is disabled) and the
content of watch register is 0000H.
c) Inputs D0 to D7 (a change on any of these inputs
or an impedance detection).
The Watchdog timer and the VL timer are disabled in
the standby mode.
2. Run mode: only the Watchdog timer (WD), an
oscillator fault, a missed I2 C-bus communication and
the reset input (RES) can trigger a reset pulse. It is
possible to enter the standby mode via control register
bit 0; see Table 8.
LED control
The dynamic mode or wait mode is possible but can only
be started from the run mode (see Section “VL timer”).
The I2C-bus interface control (see Table 10) for the LED
contains:
• Two function control bits
• Two control bits for the blink LED frequency
• Two control bits for the blink LED duration time.
All bits are combined within the LED register.
2004 Jan 15
5
PANASONIC [ PANASONIC ]
