Philips Semiconductors
Product specification
On/off logic IC
SAA1305T
Write mode operations
The transfer is terminated when the master generates a
STOP condition. In the event of a wrong address decoding
the IC sends a no acknowledge signal and ignores all
following data.
After a START condition the master sends a device select
code with the R/W bit reset to logic 0; see Fig.8. The IC
acknowledge this and waits for the address byte. After the
address the master sends the corresponding data, which
is acknowledged by the IC. It is possible to continue with
the data transfer, each byte is acknowledged by the IC.
The internal byte address counter is incremented after
each data transmission.
Figure 9 shows the sequence for write data mode. Both
alarm and watch registers consist of 3 bytes. The first byte
(2 and 5) is the most significant byte. The definitions of the
bits are given in Tables 8, 10, 14 and 15.
acknowledge
acknowledge
acknowledge acknowledge
acknowledge
handbook, full pagewidth
S
DEVICE SELECT
ADDRESS
DATA 1
DATA N
P
START
condition
STOP
condition
R/W
MGR223
Fig.8 I2C-bus write mode sequence.
handbook, full pagewidth
START
DEVICE SELECT ADDRESS CONTROL LED ALARM WATCH IMPEDANCE
byte 2, 3, 4 5, 6, 7
STOP
0
1
8
MGR224
Fig.9 I2C-bus write data sequence.
13
2004 Jan 15
PANASONIC [ PANASONIC ]
