OXCB950
OXFORD SEMICONDUCTOR LTD.
DMA[7]: Force TxRdy Inactive
7.11.12 Good-data status register ‘GDS’
logic 0 ⇒
logic 1 ⇒
TxRdy# acts normally
The GDS register is located at offset 0x10 of the ICR
TxRdy# is permanently inactive (high)
regardless of FIFO thresholds.
For the definition of Good-data status refer to section 6.4.3
GDS[0]: Good Data Status
GDS[7:1]: Reserved
7.11.14 Port Index Register ‘PIX’
The PIX register is located at offset 0x12 of the ICR. This
read-only register gives the UART index. For a single
channel device such as the OX16C950 this reads ‘0’.
7.11.13 DMA Status Register ‘DMS’
7.11.15 Clock Alteration Register ‘CKA’
The DMS register is located at offset 0x11 of the ICR. This
allows the internal TXRDY# and RXRDY# lines to be
permanently deasserted, and the current internal status to
be monitored. This mainly has applications for testing.
The CKA register is located at offset 0x13 of the ICR. This
register adds additional clock control mainly for
isochronous and embedded applications. The register is
effectively an enhancement to the CKS register.
DMS[0]: RxRdy Status
This register is cleared to 0x00 after a hardware reset to
maintain compatibility with 16C550, but is unaffected by
software reset. This allows the user to select a clock mode
and then reset the channel to work-around any timing
glitches.
Read Only: set when RxRdy is asserted (pin driven low).
DMS[1]: TxRdy Status
Read Only: set when TxRdy is asserted (pin driven low).
DMS[5:2] Reserved
DMS[6]: Force RxRdy Inactive
logic 0 ⇒
logic 1 ⇒
RxRdy# acts normally
RxRdy# is permanently inactive (high)
regardless of FIFO thresholds
DS-0033 Sep 05
External-Free Release
Page 51
OXFORD [ OXFORD SEMICONDUCTOR ]
