MT9M021, MT9M031
TYPICAL CONFIGURATION AND PINOUT
Digital
I/O
Digital
Core
HiSPi
PLL
Power
Analog
Analog
1
1
1
1
1
1
Power
Power
Power
Power
Power
V
DD
_IO
V
DD
V
DD
_SLVS
V
DD
_PLL
V
AA
V
AA
_PIX
SLVS0_P
SLVS0_N
SLVS1_P
SLVS1_N
SLVS2_P
SLVS2_N
Master Clock
(6−50 MHz)
EXTCLK
To Controller
7
S
S
DATA
SLVS3_P
7
CLK
SLVS3_N
From
Controller
OE_BAR
SLVSC_P
SLVSC_N
STANDBY
RESET_BAR
FLASH
TEST
D
A
GND
GND
Digital
Ground
Analog
Ground
V
DD
_IO
V
DD
V
DD
_SLVS
V
DD
_PLL
V
AA
V
AA
_PIX
Notes:
1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two-wire speed.
3. This pull-up resistor is not required if the controller drives a valid logic level on S at all times.
CLK
4. The parallel interface output pads can be left unconnected if the serial output interface is used.
5. ON Semiconductor recommends that 0.1 mF and 10 mF decoupling capacitors for each power supply are mounted as close as possible
to the pad. Actual values and results may vary depending on the layout and design considerations. Refer to the MT9M021/MT9M031 demo
headboard schematics for circuit recommendations.
6. ON Semiconductor recommends that analog power planes be placed in a manner such that coupling with the digital power planes is
minimized.
7. Although 4 serial lanes are shown, the MT9M021/MT9M031 supports only 2- or 3-lane HiSPi.
Figure 2. Serial 4-lane HiSPi Interface
www.onsemi.com
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