74HC574
SWITCHING WAVEFORMS
t
t
f
r
3.0 V
GND
V
CC
1.3 V
90%
50%
10%
CLOCK
GND
t
t
PLZ
PZL
t
w
HIGH
IMPEDANCE
1/f
1.3 V
max
Q
Q
10%
90%
V
V
OL
t
t
PHL
PLH
t
t
PHZ
PZH
90%
50%
10%
OH
Q
HIGH
IMPEDANCE
t
t
THL
TLH
Figure 3.
Figure 4.
TEST POINT
OUTPUT
VALID
V
DEVICE
UNDER
TEST
CC
DATA
50%
C *
L
GND
t
t
h
su
V
CC
CLOCK
50%
GND
*Includes all probe and jig capacitance.
Figure 5.
Figure 6.
C
Q
19
18
Q0
Q1
2
3
4
5
D0
D
C
Q
D1
D2
D3
D
C
Q
17
16
Q2
Q3
D
C
Q
TEST POINT
1 kW
D
CONNECT TO V WHEN
CC
OUTPUT
TESTING t
AND t
.
PLZ
PZL
C
Q
15
14
DEVICE
UNDER
TEST
Q4
Q5
6
7
CONNECT TO GND WHEN
TESTING t AND t
D4
D5
D
.
PZH
PHZ
C *
L
C
Q
D
C
Q
13
12
*Includes all probe and jig capacitance.
Q6
Q7
8
9
D6
D7
D
Figure 7. Test Circuit
C
Q
D
11
CLOCK
1
OUTPUT ENABLE
Figure 8. Expanded Logic Diagram
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