74HC574
OUTPUT
1
2
20
19
18
17
16
15
14
13
12
11
V
CC
ENABLE
D0
Q0
D1
D2
3
Q1
FUNCTION TABLE
4
Q2
Inputs
Clock
Output
OE
D
Q
D3
5
Q3
L
L
L
H
L
X
X
H
D4
6
Q4
L
No Change
Z
D5
7
Q5
L,H,
X
H
D6
8
Q6
X = Don’t Care
Z = High Impedance
D7
9
Q7
GND
10
CLOCK
Figure 1. Pin Assignment
2
3
4
5
6
7
8
19
D0
D1
D2
D3
D4
D5
D6
Q0
18
17
16
15
14
13
Q1
Q2
Q3
Q4
Q5
Q6
NONINVERTING
OUTPUTS
DATA
INPUTS
9
11
1
12
D7
Q7
CLOCK
PIN 20 = V
PIN 10 = GND
CC
OUTPUT ENABLE
Figure 2. Logic Diagram
Design Criteria
Value
Units
Internal Gate Count*
66.5
ea.
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
1.5
5.0
ns
mW
pJ
0.0075
*Equivalent to a two−input NAND gate.
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