FEDL87V5002-01
OKI Semiconductor
ML87V5002
Table 20 Descriptions of BCKO/LRCKO Cycle Register Functions
Register Name
Description
Specifies the half cycle of the BCKO.
The half cycle is specified according to the number of SYSCLK pulses.
When BCK_DIV = 0b0001, the cycle of the BCKO is 2 x SYSCLK.
When BCK_DIV = 0b0100, the cycle of the BCKO is 8 x SYSCLK.
Set BCK_DIV to 6 or less.
BCK_DIV
[3:0]
(BCK DIV * SYSCLK) * 2
BCK DIV * SYSCLK
BCK DIV * SYSCLK
BCKO
Specifies the half cycle of the LRCKO.
The half cycle is specified according to the number of BCKO pulses.
When LRCK_DIV = 0b01_0000, the cycle of the LRCKO is 32 x BCKO.
When LRCK_DIV = 0b01_1000, the cycle of the LRCKO is 64 x BCKO.
(LRCK DIV * BCKO) * 2
LRCK_DIV
[5:0]
LRCK DIV * BCKO
LRCK DIV * BCKO
LRCKO
Table 21 Examples of Setting BCK_DIV and LRCK_DIV
00
01
10
11
DO_LEN
(16 bits)
(20bits)
(24 bits)
(32 bits)
SYSCLK
512FS
Register Name
BCK_DIV
--
0100 (4)
10_0000 (32)
0100 (4)
0100 (4)
10_0000 (32)
0100 (4)
0100 (4)
LRCK_DIV
BCK_DIV
LRCK_DIV
BCK_DIV
LRCK_DIV
BCK_DIV
LRCK_DIV
BCK_DIV
LRCK_DIV
--
10_0000 (32)
0110 (6)
0011 (3)
384FS
256FS
192FS
128FS
01_0000 (16)
0100 (4)
01_1000 (24)
0010 (2)
01_1000 (24)
0010 (2)
10_0000 (32)
0010 (2)
01_0000 (16)
0011 (3)
10_0000 (32)
0010 (2)
10_0000 (32)
0010 (2)
10_0000 (32)
--
--
--
--
01_0000 (16)
0010 (2)
01_1000 (24)
--
01_1000 (24)
--
01_0000 (16)
--
--
*1: When ENBL is set to “1” with the configuration of BCK_DIV x LRCK_DIV over 192, the CFG_ERR bit is set to
“1” and the delay operation is not started.
*2: Both of the registers BCK_DIV and LRCK_DIV should be configured. The new data is valid if the both registers
are configured. For example, when only the BCK_DIV register is to be changed, the BCK_DIV register should
be configured and then the LRCK_DIV register should be configured with the value equal to the current value.
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