FEDL87V5002-01
OKI Semiconductor
ML87V5002
Operation Sequence
When reset is released, the internal register INIT( SUB:08h-bit[0] ) is set to “1” and the ML87V5002 starts the
initial sequence and then starts its normal operation.
The ML87V5002 keeps the command-wait state (waiting for the register setting of the host CPU) after the initial
sequence. In this command-wait state, the delay operation is not started and the output keeps mute states. The
delay operation is started by writing each parameter from the host CPU to the internal register and setting internal
register “ENBL” ( SUB:07h-bit[7] ) to “1”.
When internal register “ENBL” ( SUB:07h-bit[7] ) is set to “1”, the ML87V5002 starts to investigate the validity
of the settings. If the settings are proper, internal register “RUN” ( SUB:08h-bit[7] ) is set to “1”, the mute state is
released, and the delay operation is started.
• Suspension of the delay operation
This LSI sets the ENBL and RUN bits to “0” and suspends the delay operation when any of the following events
occurs:
1. “0” is written to internal register ENBL (SUB:07h-bit[7]).
2. The signals of LRCKI and BCK become out of synchronization.
3. The setting of the audio format except the delay parameters is changed.
4. Input source channel is changed.
5. Operation mode is changed.
6. The operation is started on condition that parameters at settings are not proper.
7. The BCK pulses less than the data length are input.
8. Overrun or underrun occurs due to a mismatch in clock between the input and output.
When the suspension is caused by event 2, 6, 7, or 8 above, the LSI mutes the output immediately and sets the
corresponding error bits in the internal registers shown in Table 4 to “1”.
Table 4 Error Status Registers
Register
Name
Error Description
SUB
Set when any change is detected in the input timing after resuming
the operation and the LSI suspends the delay operation.
TMG_ERR
09h-bit[7]
09h-bit[6]
Indicates the delay operation is suspended due to inconsistency of
the setting values.
CFG_ERR
BCK_ERR
Set when the number of BCK pulses in LRCK is less than the input
data length or the output data length in external synchronization 09h-bit[5]
mode after starting the operation. The delay operation is suspended.
Set when the output data cycle is slower than the input cycle and the
09h-bit[4]
OVRN
UDRN
delay buffer overflows, and the delay operation is suspended.
Set when the output data cycle is faster than the input cycle and the
09h-bit[3]
delay buffer becomes empty, and the delay operation is suspended.
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