PEDL87V21071-01
OKI Semiconductor
ML87V21071
3.5 Input Through Mode
By setting the register setting PASS (SUB:72h-bit[0]) = 1, the data (YI[7:0], CI[7:0]) and Sync. signals (IVS,
IHS) that are input to the input system pins are directly output from the output system data (YO[7:0], CO[7:0])
and Sync. signal (OVS, OHS) pins. IHS is output from HREF pin at this time.
When both the RESET pin and the OE pin are set to a Low level, a through mode is set in the same way. In this
case, input of the ICLK pin is output from the CLKO pin.
Table F3-5 Input Through Mode
Input pin
YI[7:0]
CI[7:0]
IVS
Output pin
YO[7:0]
CO[7:0]
OVS
OHS
IHS
HREF
IL Y
IH
YO[7:0]
CO[7:0]
OVS
YI[7:0]
CI[7:0]
IVS
IL Y
IH
IL Y
IH
IL Y
IH
OHS
IHS
IL Y
IH
HREF
Internal
Circuit
PASS = 0: Internal processing signal output
PASS = 1: Signal through
PASS
Figure F3-5 Input Through Mode
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