PEDL87V21071-01
OKI Semiconductor
ML87V21071
3.6 Output Enable/Disable Setting
By setting the OUTDS(SUB:72h-bit[1]) = 1, the output pins (YO[7:0], CO[7:0], OVS, OHS, HREF, CLKO) are
put in the Hi-Z state.
At system reset (external pin RESET = 0), all the output pins can be set to Enable/Disable by the external pin OE
regardless of the setting of OUTDS and output pin levels at power-on can be set.
By setting external pins OE and OEINV (SUB:72h-bit[3]), the output data pins (YO[7:0], CO[7:0]) can be put in
the Hi-Z state.
Table F3-6 Output Pin Enable/Disable Setting
RST
1
OUTDS
OE
0
OEINV
Data output pin
Disable
Output pins other than data
0
0
Enable
Enable
Enable
Enable
Disable
Disable
Enable
1
0
0
0
1
0
Enable
1
1
Enable
1
0
1
1
Disable
1
1
X
0
X
Disable
0
0 (*1)
0 (*1)
0 (*1)
0 (*1)
Disable
0
1
Enable
*1: Fixed to 0 by system reset.
3.7 Release of Synchronization by Register Setting
Normally, the data that is set through I2C interface is reflected in the IC internal section synchronously with IVS.
However, as a test mode, using the I2C-bus setting register RLTG (SUB:72h-bit[7]) can release the
synchronization. Normally, synchronize with IVS by setting the register to 0.
Table F3-7 Synchronization Release Setting by Register
RLTG
Data reflection
Synchronized with IVS
When set by I2C
0
1
69/123
OKI [ OKI ELECTRONIC COMPONETS ]
