PEDL87V21071-01
OKI Semiconductor
ML87V21071
3. Other Functions
3.1 REF Pin Output
Set the I2C-bus setting register REFSL[1:0] (SUB:60h-bit[4:3]) to select a horizontal reference signal,
chrominance select signal, or effective area signal for output from the HREF pin.
Table F3-1 REF Pin Output Selection
REFSL
REF pin output
[1]
0
[0]
0
Horizontal reference signal
Chrominance select signal
0
1
1
0
Effective area signal (horizontal reference signal + vertical blanking signal)
Output system filed pulse signal
1
1
•
Horizontal reference signal
This signal is a signal for default valid data period 1 and blanking period 0. This signal can be used as the
reference for separating Cb, Cr, etc.
0
1
2
3
4
l-1
l
l+1 l+2 l+3
OCLK
l pixels
OHS
ORE
3 pixels
m pixels
HREF
YO[7:0]
CO[7:0]
Y_BLK (00, 01, 08, 10)
C_BLK (80)
Y_BLK (00,01,08,10)
C_BLK (80)
Y0
Y1
Y2
Y3
Ym-3 Ym-2 Ym-1 Ym
Cbn-1 Crn-1 Cbn Crn
Cb0 Cr0 Cb1 Cr1
l: Set at NPHRE[7:0].
m: Set at VMD, HMD.
n: m/2
Figure F3-1 (1) Horizontal Reference Signal
Chrominance select signal
•
The chrominance select signal is a signal that toggles between 0 (at valid period start) and ICLK. It can be
used as a signal for separating Cb and Cr.
Horizontal valid data
period
OCLK
CO[7:0]
HREF
BLK
Cb Cr
Cb Cr
Cb Cr
Cb Cr
Cb Cr
BLK
Figure F3-1 (2) Chrominance Select Signal Timing
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