PEDL87V21071-01
OKI Semiconductor
ML87V21071
DESCRIPTION OF THE REGISTERS
The IC is equipped with 64 bytes (sub-address 40h to 7Fh) of sub-address registers (8-bit unit) that can access by
the I2C-bus interface.
Write cycle of the I2C-bus interface returns acknowledge by sub-addresses from 40h to 7Fh.
Regarding the read-only sub-addresses, acknowledge is returned but data write is not performed.
Settings such as mode setting, noise reduction function, memory control function, Sync. signals generation
become possible by accessing these registers.
All writable registers become readable also.
The subaddress registers 40h to 7Fh of this IC are set to the initial values of the register map as a result of input of
system reset (RESET pin = 0). For the reserved registers that are not included in the register map, 00h data is set
as the initial value.
Note: Blank (reserved) registers must be set to 0.
72/123
OKI [ OKI ELECTRONIC COMPONETS ]
