PEDL87V21071-01
OKI Semiconductor
ML87V21071
3.3 Output Signal Level Range Settings
ITU-R601 compliance is specified for the input signal level range for this IC. Output is normally the same as
input, but where 00h and FFh are input for the valid data period, you can set the output signal level range to be 01h
to FEh by setting the I2C-bussettings register R601(SUB:40h-bit[6]) = 1.
Table F3-3 Output Signal Level Range
R601
Output signal level
range
0
1
00h to FFh
01h to FEh
3.4 CLKO Output Setting
As a data latch for post-stage ICs of this IC, the CLKO pin can output a clock synchronized with data. Enable
control of the CLKO pin is possible with CKEN (SUB:60h-bit[7]).
In normal mode, ICLK is output. When TEST7 is set to 1, IICLK (same as 16-bit mode: ICLK; 8-bit or ITU-R
BT.656 mode:1 /2 division of ICLK) or ICLK can be selected in CKSL (SUB:60h-bit[6]).
Further, by setting CKINV (SUB:60h-bit[5]) as necessary, the polarity of the CLKO output clock can be inverted.
Table F3-4 CLKO Output
CKEN
CKSL
CKINV
CLKO output
Hi-Z
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
IICLK
IICLK inversion
ICLK
ICLK inversion
* In the 16-bit input mode, IICLK = ICLK.
tCKD
ICLK
[CKINV=0]
CLKO
[CKINV=1]
CLKO
Figure F3-4 (1) CLKO Output Timing (16-Bit Mode)
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