PEDL87V21071-01
OKI Semiconductor
ML87V21071
Table F4 (2) Description of the I2C-bus Format
Symbol
Description
Start condition
S
Sr
Restart condition
Slave Address W Slave address 1011_1XX0 (XX is set externally.)
Slave Address R
Slave address 1011_1XX1 (XX is set externally.)
Acknowledge (Slave side generates.)
Acknowledge (Master side generates.)
Sub-address byte
A(s)
A(m)
Sub Address
Data n
P
Data byte
Stop condition
As mentioned above, it is possible to read/write data at successive sub-addresses starting from a certain
sub-address (continuous read/write). Read/write to a non-contiguous sub-address is performed by repeating
the acknowledge and stop conditions of input format (single read/write) of the above-mentioned data 0.
The IC does not return acknowledge in the following cases:
Slave-address does not match.
Non-existing sub-address is specified.
The input timing diagram is shown below.
SDA
SCL
MSB
1
2
7
8
9
ACK
1
2
9
ACK
S
3-8
P
3-6
Start Condition
Data Line Stable: Data Valid
Stop Condition
Change of Data Allowed
Figure F4 I2C-bus Interface Basic Timing
• Setting internal reflect timing
Input System: IVS fall position (IVSINV = 0) or IVS rise position (IVSINV = 1).
* Settings by I2C-bus interface should be made by avoiding the position of above-mentioned setting internal
reflect timing. If the setting is performed at a position that contains the above timing, the setting may not finish
inside the same field.
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