FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
PCM interface
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60°C unless otherwise specified)
Parameter
Bit clock frequency
Bit clock duty ratio
Symbol
fBCLK
dBCLK
Condition
Min.
–0.1%
45
Typ.
2.048 +0.1%
50
8
Max.
Unit
MHz
%
CDL = 20 pF (during output)
CDL = 20 pF (during output)
CDL = 20 pF (during output)
CDL = 20 pF (during output)
BCLK = 2.048 MHz At output
BCLK to SYNC (during output)
SYNC to BCLK (during output)
55
+0.1%
Synchronous signal frequency fSYNC
–0.1%
kHz
dSYNC
Synchronous signal duty ratio
45
50
55
%
1
tBS
tSB
tDS
tDH
tSDX
tXD1
tXD2
tXD3
Transmit/receive synchronous
timing
Input setup time
100
100
50
50
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
PCMI pin
Input hold time
—
100
100
100
100
Digital output delay time
Digital output hold time
PCMO pin
Pull-up resistance RDL = 500Ω
CDL = 50 pF
—
—
—
BCLK
0
1
2
3
4
5
6
7
8
-
16
tBS tSB
tWS
SYNC
PCMI
tDS tDH
MSB
LSB
G.711
LSB
16-bit linear
Figure 2 PCM Interface Input Timing (Long Frame)
BCLK
0
1
2
3
4
5
6
7
8
9
-
17
tBS tSB
tWS
SYNC
PCMI
tDS tDH
MSB
LSB
G.711
LSB
16-bit linear
Figure 3 PCM Interface Input Timing (Short Frame)
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