FEDL7033-02
ML7033
1
Semiconductor
Control Registers Functional Description
CR0 (Basic operating mode)
B7
B6
B5
B4
B3
LIN
0
B2
ALAW
0
B1
MODE1
0
B0
MODE0
0
CR0
FILTER1SEL FILTER2SEL MCKSEL SHORT
default
0
0
0
0
B7
… Transmit and receive filter select for CH1
0 : ITU-T G.714 filter 1 : wideband filter for V.90 data modem application
B6
… Transmit and receive filter select for CH2
0 : ITU-T G.714 filter
1 : wideband filter for V.90 data modem application
B5
B4
… MCK frequency select
0 : 2.048 MHz 1 : 4.096 MHz
… Frame synchronizing scheme select 0 : Long frame SYNC 1 : Short frame SYNC
Refer to Figure 3.
B3
… PCM companding law select
0 : 8-bit PCM mode
1 : 14-bit linear PCM (2’s complement) mode
“1” is selected, a setting with the ALAW (CR0-B2) bit is ignored.
B2
… PCM companding law select 0 : µ-law 1 : A-law
When the LIN (CR0-B3) is “1”, a setting with this bit is ignored.
… Power saving control
B1, B0
0 : Power saving mode 1 : Normal operation
The MODE1 (CR0-B1) bit is for channel 2, and the MODE0 (CR0-B0) bit is for channel 1.
In power saving mode, power for the corresponding channel is turned off except for the last
output stage of the PCMOUT pin. The power saving mode differs from the power-down
mode controlled by the PDN pin in the following aspects;
-
-
Possible to control a state for an individual channel independently
The last stage of the PCMOUT pin is operational, and outputs ‘positive zero’ PCM code
in the 8-bit PCM mode or ‘zero’ PCM code in the 14-bit Linear PCM mode during the
assigned time slot.
-
Debounce timer and hold timer are valid.
As in power-down mode, the power saving mode does not initialize control registers and
read and write of control registers are possible in the power saving mode. The power-down
mode setting by the PDN pin takes precedence over the power saving mode.
Table 7 Mode Settings for CH1 and CH2
Power of Channel
MODE1 MODE0
PDN
RESET
Register
bit
0*1
0*1
0/1
0
bit
0*1
0*1
0/1
0
pin
pin
CH2
OFF
OFF*2
OFF
OFF*2
OFF*2
ON
CH1
OFF
OFF*2
OFF
OFF*2
ON
0
1
0
1
1
1
1
0
0
1
1
1
1
1
Initialized to default
Initialized to default
Read/Write possible
Read/Write possible
Read/Write possible
Read/Write possible
Read/Write possible
0
1
1
0
OFF*2
ON
1
1
ON
*1 forced to be default by the RESET pin = logic “0”.
*2 The last output stage is powered.
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