FEDL7033-02
ML7033
1
Semiconductor
CR4 (Debounced timer setting)
B7
B6
B5
B4
B3
B2
B1
B0
DET2
TIM3
DET2
TIM2
DET2
TIM1
DET2
TIM0
DET1
TIM3
DET1
TIM2
DET1
TIM1
DET1
TIM0
CR4
default
0
0
0
0
0
0
0
0
B7 to B4
B3 to B0
… Debounce timer setting for CH2
… Debounce timer setting for CH1
To avoid the unintended detection of glitches on the DETn signal, the ML7033 is equipped with
a debounce timer to hold the DETn (CR6-B1/CR13-B1) bit and the INT output state for a set
period, even when the state of the DETn pin changes from logic “1” to logic “0”. Bits B7 to B4
determine the debounce timer setting for CH2. Bits B3 to B0 determine the debounce timer
setting CH1.
The debounce timer is operational only in the power-on state when the PDN pin = logic “1”,
and remains operational in the power-saving mode with the MODEn (CR0-B1, B0) bits = “0” as
long as the device is in the power-on state.
The debounce timer holding time ranges from 0 ms to 225 ms at 15 ms intervals for each
individual channel. The values written into B7 to B4 (channel 2) or B3 to B0 (channel 1)
determine the holding time for each channel.
The timer value is calculated by the equation of [Decimal(B7,B6,B5,B4) * 15] or
[Decimal(B3,B2,B1,B0) * 15]. Refer to Table 8.
Table 8 Debounce Timer Setting
B7/B3
B6/B2
B5/B1
B4/B0
Timer (ms)
0
0
0
0
0
:
0
0
0
0
1
:
0
0
1
1
0
:
0
1
0
1
0
:
0
15
30
45
60
:
0
1
1
:
1
0
0
:
1
0
0
:
1
0
1
:
105
120
135
:
1
1
1
1
225
30/51
OKI [ OKI ELECTRONIC COMPONETS ]
