FEDL7033-02
ML7033
1
Semiconductor
Power-On Sequence
While in the power-on state, the following chart is recommended.
<NOTE>
POWER OFF
As the ML7033 is equipped with a power-on
reset function, initialization of the control
registers automatically occurs as the power is
turned on, even with the RESET pin = logic “1”.
However, if any of input pins are not in a high
impedance state, the power-on reset may not
function properly.
Power supply on
<Recommendation>
PDN pin = logic “0”, RESET pin= “0”
Keep the input to the RESET pin in the logic “0”
state for 100ns or longer before changing to a
logic “1”.
RESET pin = “0” to “1”
(or Power-on Reset Function)
Control Register Setting
(CH1/CH2)
Even during power-down mode with the PDN
pin = logic “0”, the SLIC interface registers
(CR6, CR13) and the INT pin are working. Data
set in other registers becomes valid after the
PDN pin is driven to a logic “1” state.
PDN pin = “1”
Normal Operation
Figure 10 Power-on Sequence Flow Chart
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