FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
External memory controller
Controls access of externally connected devices such as ROM (FLASH), SRAM, SDRAM (EDO DRAM), IO
devices, and internal FLASH memory.
(1) ROM (FLASH) access function
Supports 16-bit devices
: 1 bank
Supports FLASH memory: Byte write (can be written only by IF equivalent to SRAM).
In ML67Q5002/ML67Q5003, control internal FLASH access.
Configurable access timing.
(2) SRAM access function
Supports 16-bit devices
: 1 bank
Supports asynchronous SRAM
Configurable access timing.
(3) DRAM access function
Supports 16-bit device
: 1 bank
Supports EDO/SDRAM
made.
: Simultaneous connections to EDO-DRAM and SDRAM cannot be
Configurable access timing.
(4) External IO access function
Supports 8-bit/16-bit access
Each bank has two chip selects
Supports external wait input
: 2 banks
: Independent configuration for each bank
: XIOCS_N[3:0]
: XWAIT
Access Timing configurable for each bank independently
Power Management
HALT, STANDBY, clock gear, clock control functions are supported as power save functions.
(1) HALT mode
HALT object
CPU, internal RAM, AHB bus control
HALT mode setting: Set by the system control register.
Exit HALT mode due to: Reset, interrupt
(2) STANDBY mode
Stops the clock of entire LSI.
STANDBY mode setting: Specified by the system control register.
Exit STANDBY mode due to: Reset, external interrupt (other than EFIQ_N)
(3) Clock gear
This LSI has two clock systems, HCLK and CCLK. Configure HCLK and CCLK frequency.
HCLK: CPU, bus control, synchronous serial interface, I2C.
CCLK: Timers, PWM, UART, AD converter, etc.
(4) Clock control by each function unit
AD converter, PWM, Timers, DRAMC, DMAC, UART(FIFO), UART, Synchronous SIO, I2C.
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