FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
DESCRIPTION OF FUNCTIONS
CPU
CPU core:
ARM7TDMI
Operating frequency:
Byte ordering:
1 MHz to 60 MHz
Little endian
Instructions:
ARM instruction (32-bit length) and Thumb instruction (16-bit length) can be mixed.
General register bank:
Built-in barrel shifter:
Multiplier:
31 × 32 bits
ALU and barrel shift operations can be executed by one instruction.
32 bits × 8 bits (Modified Booth’s Algorithm)
Built-in debug function: JTAG interface, break point register
Built-in Memory
FLASH ROM:
ML675001 : ROM-less version
ML67Q5002 : 256Kbytes (128K x 16 bits)
ML67Q5003 : 512Kbytes (256K x 16 bits)
Access timing of this FLASH memory is configured by the ROM bank control register
of the external memory controller.
RAM:
32KB (8K x 32bits)
Read/Write access(8/16/32bit):3 cycle (cache memory unused)
Cache memory:
8K unified memory with 4way set-associative
Interrupt Controller
Fast interrupt request (FIQ) and interrupt request (IRQ) are employed as interrupt input signals. The interrupt
controller controls these interrupt signals going to ARM core.
(1) Interrupt sources
FIQ: 1 external source (external pin: EFIQ_N)
IRQ: total of 27 sources. 23 internal sources, and 4 external sources (external pins: EXINT[3:0])
(2) Interrupt priority level
Configurable, 8-level priority for each source
(3) External interrupt pin input
EXINT[3:0] can be set as Level or Edge sensing.
Configurable High or Low when Level sensing. Configurable Rise or Falling edge triggering when Edge
sensing.
EFIQ_N is set as Falling edge triggering.
Timers
7 channels of 16-bit reload timers are employed. Of these, 1 channel is used as system timer for OS.
The timers of other 6 channels are used in application software.
(1) System timer: 1 channel
16-bit auto reload timer: Used as system timer for OS. Interrupt request by timer overflow.
(2) Application timer: 6 channels
16-bit auto reload timer. Interrupt request by compare match.
One shot, interval
Clock can be independently set for each channel
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