FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
Primary /
Pin Name
I/O
Description
Logic
Secondary
I2C
SDA
I/O I2C Data. This pin operates as NMOS Open drain. Connect pull-up
resistor.
Secondary
Secondary
Positive
—
SCL
O
I2C Clock. This pin operates as NMOS Open drain. Connect pull-up
resistor.
Synchronous SIO
SCLK
SDI
I/O Serial clock
Secondary
Secondary
Secondary
—
I
Serial receive data
Positive
Positive
SDO
O
Serial transmit data
PWM signals
PWMOUT[0]
PWMOUT[1]
O
O
PWM output of CH0
PWM output of CH1
Secondary
Secondary
Positive
Positive
Analog-to-digital converter
AIN[0]
I
I
I
I
I
I
Ch0 analog input
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AIN[1]
Ch1 analog input
AIN[2]
Ch2 analog input
AIN[3]
Ch3 analog input
VREFP
VREFN
AVDD
Analog-to-digital converter convert reference voltage
Analog-to-digital converter convert reference GND
Analog-to-digital converter power supply
Analog-to-digital converter ground
AGND
Interrupt signals
EXINT[3:0]
I
I
External interrupt input signals
Secondary
Secondary
Positive /
Negative
EFIQ_N
External fast interrupt input signal.
Negative
Interrupt controller connects this to CPU FIQ input.
MODE configuration
DRAME_N
TEST
I
I
I
I
I
DRAM enable mode
—
—
—
—
—
Negative
Positive
Positive
Positive
—
Test mode
TEST1
Test mode
FWR
Test mode
JSEL
JTAG select signal. L: On-board debug, H: Boundary scan.
Power supplies
VDD_CORE
VDD_IO
Core power supply
I/O power supply
GND for core and I/O
PLL power supply
GND for PLL
—
—
—
—
—
—
—
—
—
—
GND
PLLVDD
PLLGND
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OKI [ OKI ELECTRONIC COMPONETS ]
