PEDL60851C-02
1
Semiconductor
ML60851C
End Point 0 Status Register (EP0STAT)
Read address
Write address
F3h
73h
D7
0
D6
0
D5
0
D4
0
D3
0
D2
x
D1
0
D0
0
After a hardware reset
After a bus reset
Definition
0
0
0
0
0
x
0
0
0
0
0
0
Setup Ready (R/Reset)
Stall Bit (R/W)
EP0 Stage (R)
00 = Setup stage
01 = Data stage
10 = Status stage
Setup Ready:
This bit is set automatically when a proper setup packet arrives in the 8-byte setup register, and
the EP0RXFIFO is locked. If D0 of INTENBL has been asserted, the INTR pin is also
asserted automatically when this bit is set. The local MCU should write a “1” in this bit after
the reading out the 8-byte setup data. When this is performed, the setup ready bit is reset and
the INTR pin also is deasserted. During a control write, even the packet ready bit of EP0 is
reset simultaneously, the lock condition is released, and it becomes possible to receive packets
by EP0 during the data stage.
The register value will not change even if a “0” is written in this bit.
Stall bit: During EP0 reception (in the data stage of a control write transfer), the ML60851C
automatically sets this bit to “1” when a packet with a number bytes more than the maximum
packet size written in EP0RXPLD is received (or when EOP is missing).
Bits D7 to D5 and D1 are fixed at “0”, and other values written in them are invalid.
EP0 Stage:
Indicates the stage transition during a control transfer. The transition conditions between the
different stages are shown in the following stage transition diagram.
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