PEDL60851C-02
1
Semiconductor
ML60851C
End Point 2 Control Register (EP2CON)
Read address
Write address
F4h
74
D7
0
D6
0
D5
1
D4
0
D3
1
D2
0
D1
X
D0
0
After a hardware reset
After a bus reset
Definition
0
0
1
0
1
0
X
0
0
1
0
1
0
Configuration Bit (R/W)
Stall Bit (R/W)
Transfer Type
10 = Bulk transfer
End Point Address (R)
Transfer Direction (R/W)
0 = Receive, 1 = Transmit
Configuration Bit: The local MCU should write a “1” in this bit during the status stage of control transfer when a
“Set Configuration” request is received from the host computer to make EP2 active. When this
bit is “1”, the exchange of data between the host computer and EP2 is enabled. When this bit is
“0”, this IC does not respond to any transactions with this EP.
Stall Bit:
During EP2 reception, when a data packet is received with a number of bytes more than the
maximum packet size set in the pay load register EP2PLD, the ML60851C automatically sets
this bit to “1”. It is also possible for the local MCU to write a “1” in this bit. When this bit is
“1”, the stall handshake is automatically returned to the host computer in response to the packet
transmitted by the host computer to the end point. In addition, the packet ready status is not
asserted and the INTR pin is not asserted.
The EP2 transfer mode is set as a bulk transfer and the end point address is 2h. Therefore, the bits D6 to D2 have
fixed values, and other values written in them are ignored.
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