––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ ML53612 ■
4.14 CT_D disable
The user may disable all CT_D output streams in the event of a bus timing error. When enabled, an error
on the slave PLL reference source causes the CT_D streams to be tri-stated until an entire frame time
without errors has passed. The CT_D_DISABLE signal is provided to link multiple ML53612 devices.
4.15 Diagnostic Mode
Diagnostic mode tri-states all CT Bus signals while internally looping-back CT Bus outputs to inputs.
This mode allows a printed circuit board containing the ML53612 to be thoroughly tested without
causing CT Bus errors.
4.16 Interrupts
The ML53612 supports the following interrupt sources:
• CT Bus A Error
• CT Bus B Error
CT Bus A (CT Bus B) error is detected when CT_C8_A (CT_C8_B) rising edge does not occur within
35 ns of the expected time, relative to the previous period (see Figure 4) or when CT_FRAME_A_N
(CT_FRAME_B_N) low does not occur when expected. (See ECTF H.100/H.110 Specifications for
details on CT_C8_(A/B) and CT_FRAME_(A/B)_N signal timing.)
• SCbus Error
SCbus error is detected when SCLK does not transition at close to the expected frequency (C_[25:24]
determines the expected frequency) or FR_COMP_N low does not occur when expected. (See ECTF
H.100/H.110 Specifications for details on SCLK, SCLKx2, and FR_COMP_N signal timing.)
• MVIP Error
MVIP error is detected when C2 does not transition at close to 2 MHz, or FR_COMP_N low does not
occur when expected. (See ECTF H.100/H.110 Specifications for details on C2 and FR_COMP_N sig-
nal timing).
• Master PLL Out of Lock Error
Master PLL error is detected when the master PLL is not locked to the selected Reference defined by
C_[43:40].
• Frame Boundary
Frame Boundary interrupt is not an error condition, and occurs when the internal state machine
crosses a frame boundary.
• GPIO
GPIO interrupt occurs when one or more of the GPIO inputs match the programmed latch polarity,
defined by C_[167:136].
The interrupts are both globally and individually maskable, and are signaled to the processor via the INT
pin (pin 10). The INT pin can be configured to operate as either push-pull or open drain, and its polarity
(active high or active low) is also selectable.
All of these interrupt latches have an individual enable/clear register and an individual interrupt mask
register associated with them.
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